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specifications isplsi and plsi 1032 1 1996 isp encyclopedia 1032_02 functional block diagram output routing pool output routing pool d7 d6 d5 d4 d3 d2 d1 d0 b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 c7 c6 c5 c4 c3 c2 c1 c0 output routing pool clk output routing pool global routing pool (grp) logic array dq dq dq dq glb description the isplsi and plsi 1032 are high-density program- mable logic devices containing 192 registers, 64 universal i/o pins, eight dedicated input pins, four dedi- cated clock input pins and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 1032 features 5-volt in- system programming and in-system diagnostic capabilities. it is the first device which offers non-volatile "on-the-fly" reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. it is architecturally and parametrically compatible to the plsi 1032 device, but multiplexes four of the dedicated input pins to control in-system programming. the basic unit of logic on the isplsi and plsi 1032 devices is the generic logic block (glb). the glbs are labeled a0, a1 .. d7 (see figure 1). there are a total of 32 glbs in the isplsi and plsi 1032 devices. each glb has 18 inputs, a programmable and/or/xor array, and four outputs which can be configured to be either combi- natorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any other glb on the device. features ? high-density programmable logic high speed global interconnect 6000 pld gates 64 i/o pins, eight dedicated inputs 192 registers wide input gating for fast counters, state machines, address decoders, etc. small logic block size for fast random logic security cell prevents unauthorized copying ? high performance e 2 cmos ? technology f max = 90 mhz maximum operating frequency f max = 60 mhz for industrial and military/883 devices t pd = 12 ns propagation delay ttl compatible inputs and outputs electrically erasable and reprogrammable non-volatile e 2 cmos technology 100% tested ? isplsi offers the following added features in-system programmable? (isp?) 5-volt only increased manufacturing yields, reduced time-to- market, and improved product quality reprogram soldered devices for faster prototyping ? combines ease of use and the fast system speed of plds with the density and flex- ibility of field programmable gate arrays complete programmable device can combine glue logic and structured designs four dedicated clock input pins synchronous and asynchronous clocks flexible pin placement optimized global routing pool provides global interconnectivity ? isplsi and plsi development tools pds ? software easy to use pc windows? interface boolean logic compiler manual partitioning automatic place and route static timing table ispds+? software industry standard, third party design environments schematic capture, state machine, hdl automatic partitioning and place and route comprehensive logic and timing simulation pc and workstation platforms isplsi ? and plsi ? 1032 high-density programmable logic copyright ? 1997 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. february 1997 tel. (503) 681-0118; 1-800-lattice; fax (503) 681-3037; http://www.latticesemi.com 1996 isp encyclopedia
specifications isplsi and plsi 1032 2 1996 isp encyclopedia functional block diagram figure 1. isplsi and plsi 1032 functional block diagram the devices also have 64 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional i/o pin with 3-state control. additionally, all outputs are polarity selectable, active high or active low. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. eight glbs, 16 i/o cells, two dedicated inputs and one orp are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 16 universal i/o cells by the orp. the i/o cells within the megablock also share a common output enable (oe) signal. the isplsi and plsi 1032 devices contain four of these megablocks. the grp has as its inputs the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi and plsi 1032 devices are selected using the clock distribution network. four dedicated clock pins (y0, y1, y2 and y3) are brought into the distribution network, and five clock outputs (clk 0, clk 1, clk 2, ioclk 0 and ioclk 1) are provided to route clocks to the glbs and i/o cells. the clock distribution network can also be driven from a special clock glb (c0 on the isplsi and plsi 1032 devices). the logic of this glb allows the user to create an internal clock from a combination of internal signals within the device. y 0 y 1 y 2 y 3 i/o 0 i/o 1 i/o 2 i/o 3 in 5 in 4 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 *sdi/in 0 *mode/in 1 i/o 62 i/o 63 i/o 61 i/o 60 i/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 7 in 6 i/o 17 i/o 16 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 *sdo/in 2 *sclk/in 3 i/o 4 i/o 5 reset global routing pool (grp) output routing pool (orp) output routing pool (orp) clk 0 clk 1 clk 2 ioclk 0 ioclk 1 clock distribution network d7 d6 d5 d4 d3 d2 d1 d0 b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 c7 c6 c5 c4 c3 c2 c1 c0 output routing pool (orp) generic logic blocks (glbs) megablock output routing pool (orp) input bus input bus input bus *ispen/nc lnput bus *isp control functions for isplsi 1032 only 0139(1)-32-isp
specifications isplsi and plsi 1032 3 1996 isp encyclopedia absolute maximum ratings 1 supply voltage v cc ...................................-0.5 to +7.0v input voltage applied ........................ -2.5 to v cc +1.0v off-state output voltage applied ..... -2.5 to v cc +1.0v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating conditions v v parameter symbol min. max. units 5.25 5.5 5.5 0.8 v cc + 1 supply voltage v cc v il v ih table 2- 0005aisp w/mil.eps 4.75 4.5 4.5 0 2.0 commercial t a = 0 c to +70 c industrial t a = -40 c to +85 c military/883 t c = -55 c to +125 c input low voltage input high voltage v capacitance (t a =25 o c, f=1.0 mhz) symbol parameter maximum 1 units test conditions c 1 commercial/industrial 8 pf v cc =5.0v, v in =2.0v military 10 pf v cc =5.0v, v in =2.0v c 2 i/o and clock capacitance 10 pf v cc =5.0v, v i/o , v y =2.0v 1 . guaranteed but not 100% tested. table 2- 0006 dedicated input capacitance data retention specifications table 2- 0008b parameter plsi erase/reprogram cycles 100 data retention minimum maximum units isplsi erase/reprogram cycles 20 10000 cycles years cycles
specifications isplsi and plsi 1032 4 1996 isp encyclopedia switching test conditions input pulse levels gnd to 3.0v input rise and fall time 3ns 10% to 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure 2 3-state levels are measured 0.5v from steady-state active level. table 2 - 0003 output load conditions (see figure 2) test condition r1 r2 cl a 470 w 390 w 35pf b active high 390 w 35pf active low 470 w 390 w 35pf active high to z 390 w 5pf cat v oh - 0.5v active low to z 470 w 390 w 5pf at v ol + 0.5v figure 2. test load + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. dc electrical characteristics over recommended operating conditions 0.4 C -10 10 -150 -150 -200 190 220 v v m a m a m a m a ma ma ma symbol v ol v oh i il i ih i il-isp i il-pu i os 1 i cc 2,4 output low voltage output high voltage input or i/o low leakage current input or i/o high leakage current isp input low leakage current i/o active pull-up current output short circuit current operating power supply current i ol =8 ma i oh =-4 ma 0v v in v il (max.) 3.5v v in v cc 0v v in v il (max.) 0v v in v il v cc = 5v, v out = 0.5v v il = 0.5v, v ih = 3.0v commercial f toggle = 1 mhz industrial/military parameter condition min. units max. typ. 3 C C C C C C C 130 135 C 2.4 C C C C C C C 1. one output at a time for a maximum duration of one second. 2. measured using eight 16-bit counters. 3. typical values are at v cc = 5v and t a = 25 o c. 4. maximum i cc varies widely with specific device configuration and operating frequency. refer to the power consumption sec- tion of this datasheet and thermal management section of this data book to estimate maximum i cc . table 2- 0007a-32-isp
specifications isplsi and plsi 1032 5 1996 isp encyclopedia use 1032e-80 for new designs use 1032e-70 for new designs external timing parameters over recommended operating conditions 1. unless noted otherwise, all parameters use a grp load of 4 glbs, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. f max (toggle) may be less than 1/( t wh + t wl). this is to allow for a clock duty cycle of other than 50%. 5. reference switching test conditions section. min. max. data propagation delay, 4pt bypass, orp bypass data propagation delay, worst case path clock frequency with internal feedback 3 clock frequency with external feedback clock frequency, max toggle 4 glb reg. setup time before clock, 4pt bypass glb reg. clock to output delay, orp bypass glb reg. hold time after clock, 4 pt bypass glb reg. setup time before clock glb reg. clock to output delay glb reg. hold time after clock ext. reset pin to output delay ext. reset pulse duration input to output enable input to output disable ext. sync. clock pulse duration, high ext. sync. clock pulse duration, low i/o reg. setup time before ext. sync. clock (y2, y3) i/o reg. hold time after ext. sync. clock (y2, y3) ns ns mhz mhz mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns t pd1 t pd2 f max (int.) f max (ext.) f max (tog.) t su1 t co1 t h1 t su2 t co2 t h2 t r1 t rw1 t en t dis t wh t wl t su5 t h5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 a a a a a b c description 1 parameter # 2 units test 5 cond. 1 tsu2 + tco1 ( ) min. max. 80 50 100 7 0 10 0 10 5 5 2 6.5 15 20 10 12 17 18 18 60 38 83 9 0 13 0 13 6 6 2.5 8.5 20 25 13 16 22.5 24 24 -80 -60 min. max. 90.9 58.8 125 6 0 9 0 10 4 4 2 6.5 12 17 8 10 15 15 15 -90 table 2-0030-32/90,80,60c
specifications isplsi and plsi 1032 6 1996 isp encyclopedia use 1032e-80 for new designs use 1032e-70 for new designs internal timing parameters 1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns C C 7.3 1.3 C C C C C C C C C C C C C C 1.3 6.0 C C C C 4.6 C C 2.7 4.0 C C 4.0 3.3 5.3 2.0 2.7 4.0 5.0 6.0 10.6 8.6 9.3 10.6 12.7 1.3 C C 2.7 3.3 13.3 12.0 9.9 3.3 0.7 min. max. description parameter units -60 inputs t iobp t iolat t iosu t ioh t ioco t ior t din grp t grp1 t grp4 t grp8 t grp12 t grp16 t grp32 glb t 4ptbp t 1ptxor t 20ptxor t xoradj t gbp t gsu t gh t gco t gr t ptre t ptoe t ptck orp t orp t orpbp # 2 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 i/o register bypass i/o latch delay i/o register setup time before clock i/o register hold time after clock i/o register clock to out delay i/o register reset to out delay dedicated input delay grp delay, 1 glb load grp delay, 4 glb loads grp delay, 8 glb loads grp delay, 12 glb loads grp delay, 16 glb loads grp delay, 32 glb loads 4 product term bypass path delay 1 product term/xor path delay 20 product term/xor path delay xor adjacent path delay 3 glb register bypass delay glb register setup time before clock glb register hold time after clock glb register clock to output delay glb register reset to output delay glb product term reset to register delay glb product term output enable to i/o cell delay glb product term clock delay orp delay orp bypass delay C C 5.5 1.0 C C C C C C C C C C C C C C 1.0 4.5 C C C C 3.5 C C 2.0 3.0 C C 3.0 2.5 4.0 1.5 2.0 3.0 3.8 4.5 8.0 6.5 7.0 8.0 9.5 1.0 C C 2.0 2.5 10.0 9.0 7.5 2.5 0.5 min. max. -80 C C 4.8 2.1 C C C C C C C C C C C C C C 1.2 3.6 C C C C 2.8 C C 1.6 2.4 C C 2.4 2.8 3.2 1.2 1.6 2.4 3.0 3.6 6.4 5.2 5.7 7.0 8.2 0.8 C C 1.6 2.0 8.0 7.8 6.0 2.4 0.4 min. max. -90 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros.
specifications isplsi and plsi 1032 7 1996 isp encyclopedia use 1032e-80 for new designs use 1032e-70 for new designs internal timing parameters 1 ns ns ns ns ns ns ns ns ns C C C 6.0 4.6 1.3 4.6 1.3 C 4.0 6.7 6.7 6.0 7.3 6.6 7.3 6.6 12.0 outputs t ob t oen t odis clocks t gy0 t gy1/2 t gcp t ioy2/3 t iocp global reset t gr 47 48 49 50 51 52 53 54 55 output buffer delay i/o cell oe to output enabled i/o cell oe to output disabled clock delay, y0 to global glb clock line (ref. clock) clock delay, y1 or y2 to global glb clock line clock delay, clock glb to global glb clock line clock delay, y2 or y3 to i/o cell global clock line clock delay, clock glb to i/o cell global clock line global reset to glb and i/o registers min. max. description parameter units -60 # 2 C C C 4.5 3.5 1.0 3.5 1.0 C 3.0 5.0 5.0 4.5 5.5 5.0 5.5 5.0 9.0 min. max. -80 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. C C C 3.6 2.8 0.8 2.8 0.8 C 2.4 4.0 4.0 3.6 4.4 4.0 4.4 4.0 8.2 min. max. -90
specifications isplsi and plsi 1032 8 1996 isp encyclopedia isplsi and plsi 1032 timing model glb reg delay i/o pin (output) orp delay feedback 4 pt bypass 20 pt xor delays control pts grp loading delay input register clock distribution i/o pin (input) y0 y1,2,3 d q grp 4 glb reg bypass orp bypass dq rst re oe ck i/o reg bypass i/o cell orp glb grp i/o cell #21 - 25 #27, 29, 30, 31, 32 #28 #33 #34, 35, 36 #51, 52, 53, 54 #42, 43, 44 #50 #45 #46 reset ded. in #26 #20 rst #55 #55 #37 #38, 39, 40, 41 #48, 49 #47 derivations of t su, t h and t co from the product term clock 1 t su = logic + reg su - clock (min) = ( t iobp + t grp4 + t 20ptxor ) + ( t gsu ) - ( t iobp + t grp4 + t ptck(min) ) = ( #20 + #28 + #35 ) + ( #38 ) - ( #20 + #28 + #44 ) 5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (2.0 + 2.0 + 3.5) t h = clock (max) + reg h - logic = ( t iobp + t grp4 + t ptck(max) ) + ( t gh ) - ( t iobp + t grp4 + t 20ptxor ) = ( #20 + #28 + #44 ) + ( #39 ) - ( #20 + #28 + #35 ) 4.0 ns = (2.0 + 2.0 + 7.5) + (4.5) - (2.0 + 2.0 + 8.0) t co = clock (max) + reg co + output = ( t iobp + t grp4 + t ptck(max) ) + ( t gco ) + ( t orp + t ob ) = ( #20 + #28 + #44 ) + ( #40 ) + ( #45 + #47 ) 19.0 ns = (2.0+ 2.0 +7.5) + (2.0) + (2.5 + 3.0) derivations of t su, t h and t co from the clock glb 1 t su = logic + reg su - clock (min) = ( t iobp + t grp4 + t 20ptxor ) + ( t gsu ) - ( t gy0(min) + t gco + t gcp(min) ) = ( #20 + #28 + #35 ) + ( #38 ) - ( #50 + #40 + #52 ) 5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (4.5 + 2.0 + 1.0) t h = clock (max) + reg h - logic = ( t gy0(max) + t gco + t gcp(max) ) + ( t gh ) - ( t iobp + t grp4 + t 20ptxor ) = ( #50 + #40 + #52 ) + ( #39 ) - ( #20 + #28 + #35 ) 4.0 ns = (4.5 + 2.0 + 5.0) + (4.5) - (2.0 + 2.0 + 8.0) t co = clock (max) + reg co + output = ( t gy0(max) + t gco + t gcp(max) ) + ( t gco ) + ( t orp + t ob ) = ( #50 + #40 + #52 ) + ( #40 ) + ( #45 + #47 ) 19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0) 1. calculations are based upon timing specifications for the isplsi and plsi 1032-80.
specifications isplsi and plsi 1032 9 1996 isp encyclopedia maximum grp delay vs glb loads isplsi and plsi 1032-80 isplsi and plsi 1032-60 isplsi and plsi 1032-90 0126a-80-32-isp 1 2 3 4 8 12 16 glb loads grp delay (ns) 4 5 6 0 power consumption used. figure 3 shows the relationship between power and operating speed. power consumption in the isplsi and plsi 1032 device depends on two primary factors: the speed at which the device is operating, and the number of product terms figure 3. typical device power consumption vs fmax 50 100 150 200 250 0 10203040506070 f max (mhz) i cc (ma) 80 notes: configuration of eight 16-bit counters typical current at 5v, 25?c isplsi and plsi 1032 0127a-32-80-isp i cc can be estimated for the isplsi and plsi 1032 using the following equation: i cc = 52 + (# of pts * 0.30) + (# of nets * max. freq * 0.009) where: # of pts = number of product terms used in design # of nets = number of signals used in device max. freq = highest clock frequency to the device the i cc estimate is based on typical conditions (v cc = 5.0v, room temperature) and an assumption of 2 glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified.
specifications isplsi and plsi 1032 10 1996 isp encyclopedia in-system programmability figure 4. isp programming interface ispgds ispgal isplsi sclk mode sclk mode sdi sdo sdo sdo sdi sdi ispen sclk mode sdo sdi mode sclk ispen 5-wire isp programming interface isplsi sclk mode sdi sdo ispen 0294 b controls the programming. the interface signals are isp enable ( ispen ), serial data in (sdi), serial data out (sdo), serial clock (sclk) and mode (mode) control. figure 4 illustrates the block diagram of one possible scheme for programming the isplsi devices. for details on the operation of the internal state machine and pro- gramming of the device please refer to the isp architecture and programming section in this data book. the device identifier for the isplsi 1032 is 0000 0011 (03 hex). this code is the unique device identifier which is generated when a read id command is performed. the isplsi devices are the in-system programmable versions of the lattice semiconductor high-density pro- grammable large scale integration (plsi) devices. by integrating all the high voltage programming circuitry on- chip, programming can be accomplished by simply shifting data into the device. once the function is programmed, the non-volatile e 2 cmos cells will not lose the pattern even when the power is turned off. all necessary programming is done via five ttl level logic interface signals. these five signals are fed into the on-chip programming circuitry where a state machine
specifications isplsi and plsi 1032 11 1996 isp encyclopedia isplsi 1032 shift register layout e 2 cmos cell array high order shift register low order shift register 159... 319... ...0 ...160 d a t a d a t a data in (sdi) sdo 107 . . . address shift register . . . 0 sdo sdi note: a logic "1" in the address shift register bit position enables the row for programming or verification. a logic "0" disables it.
specifications isplsi and plsi 1032 12 1996 isp encyclopedia pin description input C dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. the mode, sdi, sdo and sclk options become active. input C this pin performs two functions. it is a dedicated input pin when ispen is logic high. when ispen is logic low, it functions as an input pin to load programming data into the device. sdi/in 0 also is used as one of the two control pins for the isp state machine. input C this pin performs two functions. it is a dedicated input pin when ispen is logic high. when ispen is logic low, it functions as a pin to control the operation of the isp state machine. input/output C this pin performs two functions. it is a dedicated input pin when ispen is logic high. when ispen is logic low, it functions as an output pin to read serial shift register data. input C this pin performs two functions. it is a dedicated input when ispen is logic high. when ispen is logic low, it functions as a clock pin for the serial shift register. * for isplsi 1032 only name plcc pin numbers description input/output pins - these are the general purpose i/o pins used by the logic array. i/o 0 - i/o 3 26, 27, 28, 29, i/o 4 - i/o 7 30, 31, 32, 33, i/o 8 - i/o 11 34, 35, 36, 37, i/o 12 - i/o 15 38, 39, 40, 41, i/o 16 - i/o 19 45, 46, 47, 48, i/o 20 - i/o 23 49, 50, 51, 52, i/o 24 - i/o 27 53, 54, 55, 56, i/o 28 - i/o 31 57, 58, 59, 60, i/o 32 - i/o 35 68, 69, 70, 71, i/o 36 - i/o 39 72, 73, 74, 75, i/o 40 - i/o 43 76, 77, 78, 79, i/o 44 - i/o 47 80, 81, 82, 83, i/o 48 - i/o 51 3, 4, 5, 6, i/o 52 - i/o 55 7, 8, 9, 10, i/o 56 - i/o 59 11, 12, 13, 14, i/o 60 - i/o 63 15, 16, 17, 18 in 4 - in 7 67, 84, 2, 19 dedicated input pins to the device. active low (0) reset pin which resets all of the glb and i/o registers in the device. dedicated clock input. this clock input is connected to one of the clock inputs of all of the glbs on the device. dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb on the device. dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or any i/o cell on the device. dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any i/o cell on the device. ispen*/nc 23 sdi*/in 0 25 mode*/in 1 42 sdo*/in 2 44 sclk*/in 3 61 gnd 1, 22, 43, 64 v cc 21, 65 ground (gnd) v cc reset 24 y0 20 y1 66 y2 63 y3 62 table 2-0002a-32-isp
specifications isplsi and plsi 1032 13 1996 isp encyclopedia pin description input C dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. the mode, sdi, sdo and sclk options become active. input C this pin performs two functions. it is a dedicated input pin when ispen is logic high. when ispen is logic low, it functions as an input pin to load programming data into the device. sdi/in 0 also is used as one of the two control pins for the isp state machine. input C this pin performs two functions. it is a dedicated input pin when ispen is logic high. when ispen is logic low, it functions as a pin to control the operation of the isp state machine. input/output C this pin performs two functions. it is a dedicated input pin when ispen is logic high. when ispen is logic low, it functions as an output pin to read serial shift register data. input C this pin performs two functions. it is a dedicated input when ispen is logic high. when ispen is logic low, it functions as a clock pin for the serial shift register. these pins are not used. description tqfp pin numbers name input/output pins - these are the general purpose i/o pins used by the logic array. i/o 0 - i/o 3 17, 18, 19, 20, i/o 4 - i/o 7 21, 22, 23, 28, i/o 8 - i/o 11 29, 30, 31, 32, i/o 12 - i/o 15 33, 34, 35, 36, i/o 16 - i/o 19 40, 41, 42, 43, i/o 20 - i/o 23 44, 45, 46, 47, i/o 24 - i/o 27 48, 53, 54, 55, i/o 28 - i/o 31 56, 57, 58, 59, i/o 32 - i/o 35 67, 68, 69, 70, i/o 36 - i/o 39 71, 72, 73, 78, i/o 40 - i/o 43 79, 80, 81, 82, i/o 44 - i/o 47 83, 84, 85, 86, i/o 48 - i/o 51 90, 91, 92, 93, i/o 52 - i/o 55 94, 95, 96, 97, i/o 56 - i/o 59 98, 3, 4, 5, i/o 60 - i/o 63 6, 7, 8, 9 in 4 - in 7 66, 87, 89, 10 dedicated input pins to the device. ispen*/nc 14 sdi*/in 0 16 mode*/in 1 37 sdo*/in 2 39 sclk*/in 3 60 nc 1, 2, 24, 25, 26, 27, 49, 50, 51, 52, 74, 75 76, 77, 99, 100 active low (0) reset pin which resets all of the glb and i/o registers in the device. dedicated clock input. this clock input is connected to one of the clock inputs of all of the glbs on the device. dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb on the device. dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or any i/o cell on the device. dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any i/o cell on the device. reset 15 y0 11 y1 65 y2 62 y3 61 gnd 13, 38, 63, 88 v cc 12, 64 ground (gnd) v cc table 2- 0002b-32-isp * for isplsi 1032 only
specifications isplsi and plsi 1032 14 1996 isp encyclopedia pin description reset g1 y0 e1 y1 e11 y2 g9 y3 g11 nc g3 gnd c6, f3, f9, j6 v cc f2, f11 i/o 0 - i/o 3 f1, h1, h2, j1, i/o 4 - i/o 7 k1, j2, l1, k2, i/o 8 - i/o 11 k3, l2, l3, k4, i/o 12 - i/o 15 l4, j5, k5, l5, i/o 16 - i/o 19 l7, k7, l6, l8, i/o 20 - i/o 23 k8, l9, l10, k9, i/o 24 - i/o 27 l11, k10, j10, k11, i/o 28 - i/o 31 j11, h10, h11, f10, i/o 32 - i/o 35 e9, d11, d10, c11, i/o 36 - i/o 39 b11, c10, a11, b10, i/o 40 - i/o 43 b9, a10, a9, b8, i/o 44 - i/o 47 a8, b6, b7, a7, i/o 48 - i/o 51 a5, b5, c5, a4, i/o 52 - i/o 55 b4, a3, a2, b3, i/o 56 - i/o 59 a1, b2, c2, b1, i/o 60 - i/o 63 c1, d2, d1, e3 in 4 - in 7 e10, c7, a6, e2 dedicated input pins to the device. input/output pins - these are the general purpose i/o pins used by the logic array. name cpga pin numbers description input C dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. the mode, sdi, sdo and sclk options become active. input C this pin performs two functions. it is a dedicated input pin when ispen is logic high. when ispen is logic low, it functions as an input pin to load programming data into the device. sdi/in 0 also is used as one of the two control pins for the isp state machine. input C this pin performs two functions. it is a dedicated input pin when ispen is logic high. when ispen is logic low, it functions as a pin to control the operation of the isp state machine. input/output C this pin performs two functions. it is a dedicated input pin when ispen is logic high. when ispen is logic low, it functions as an output pin to read serial shift register data. input C this pin performs two functions. it is a dedicated input when ispen is logic high. when ispen is logic low, it functions as a clock pin for the serial shift register. ispen*/nc g3 sdi*/in 0 g2 mode*/in 1 k6 sdo*/in 2 j7 sclk*/in 3 g10 active low (0) reset pin which resets all of the glb and i/o registers in the device. dedicated clock input. this clock input is connected to one of the clock inputs of all of the glbs on the device. dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb on the device. dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or any i/o cell on the device. dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any i/o cell on the device. this pin should be left floating or tied to v cc. this pin should never be tied to gnd. ground (gnd) v cc table 2-0002-32/883
specifications isplsi and plsi 1032 15 1996 isp encyclopedia pin configuration isplsi and plsi 1032 84-pin plcc pinout diagram i/o 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 in 4 y1 vcc gnd y2 y3 in 3/sclk* i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 in 7 y0 vcc gnd *ispen/nc reset *sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 6 gnd in 5 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 *mode/in 1 gnd *sdo/in 2 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 isplsi 1032 plsi 1032 top view *pins have dual function capability for isplsi 1032 only (except pin 23, which is ispen only). 0123-32-isp
specifications isplsi and plsi 1032 16 1996 isp encyclopedia nc nc i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 in 7 y0 vcc gnd *ispen/nc reset *sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 nc nc nc nc i/o 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 in 4 y1 vcc gnd y2 y3 in 3/sclk* i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 nc nc nc nc i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 6 gnd in 5 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 nc nc nc nc i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 *mode/in1 gnd *sdo/in 2 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 58 isplsi 1032 plsi 1032 top view *pins have dual function capability for isplsi 1032 only (except pin 14, which is ispen only). 0766a-32-isp pin configuration isplsi and plsi 1032 100-pin tqfp pinout diagram
specifications isplsi and plsi 1032 17 1996 isp encyclopedia i /o38 i /o36 i /o35 i /o33 y1 vcc y3 i /o30 i /o28 i /o27 i /o24 i /o41 i /o39 i /o37 i /o34 i n4 i /o31 *sclk/ i n3 i /o29 i /o26 i /o25 i /o22 i /o42 i /o40 i /o32 gnd y2 i /o23 i /o21 i /o44 i /o43 i /o20 i /o19 i /o47 i /o46 i n5 *sdo/ i n2 i /o17 i /o16 i n6 i /o45 gnd gnd *mode/ i n1 i /o18 i /o48 i /o49 i /o50 i /o13 i /o14 i /o15 i /o51 i /o52 i /o11 i /o12 i /o53 i /o55 index i /o63 gnd *ispen /nc i /o8 i /o10 i /o54 i /o57 i /o58 i /o61 i n7 vcc *sdi/ i n0 i /o2 i /o5 i /o7 i /o9 i /o56 i /o59 i /o60 i /o62 y0 i /o0 reset i /o1 i /o3 i /o4 i /o6 isplsi 1032/883 plsi 1032/883 bottom view a b c d e f g h j k l 11 10 9 8 7 6 5 4 3 2 1 pin a1 *pins have dual function capability for isplsi 1032/883 only (except pin g3, which is ispen only). 0488a-32-isp/883 pin configuration isplsi and plsi 1032/883 84-pin cpga pinout diagram
specifications isplsi and plsi 1032 18 1996 isp encyclopedia isplsi and plsi 1032 ordering information part number description device number grade blank = commercial i = industrial /883 = 883 military process 1032 xx x x x speed 90 = 90 mhz f max 80 = 80 mhz f max 60 = 60 mhz f max power l = low package j = plcc t = tqfp g = cpga device family 0212-80b-isp1032 (is)plsi t pd (ns) f max (mhz) ordering number package 90 12 isplsi 1032-90lt 100-pin tqfp 80 15 isplsi 1032-80lj 84-pin plcc commercial 90 12 isplsi 1032-90LJ 84-pin plcc 80 15 isplsi 1032-80lt 100-pin tqfp 60 20 isplsi 1032-60lj 84-pin plcc 60 20 isplsi 1032-60lt 100-pin tqfp industrial t pd (ns) f max (mhz) ordering number package 60 20 isplsi 1032-60lji 84-pin plcc family isplsi 90 12 plsi 1032-90lt 100-pin tqfp 80 15 plsi 1032-80lj 84-pin plcc 90 12 plsi 1032-90LJ 84-pin plcc 80 15 plsi 1032-80lt 100-pin tqfp 60 20 plsi 1032-60lj 84-pin plcc 60 20 plsi 1032-60lt 100-pin tqfp plsi isplsi plsi 60 20 plsi 1032-60lji 84-pin plcc family table 2- 0041a-32-isp military/883 t pd (ns) f max (mhz) ordering number package 60 20 isplsi 1032-60lg/883 84-pin cpga isplsi plsi 60 20 plsi 1032-60lg/883 84-pin cpga family smd number 5962-9308501mxc 5962-9466801mxc note: lattice semiconductor recognizes the trend in military device procurement towards using smd compliant devices, as such, ordering by this number is recommended. 60 20 isplsi 1032-60lti 100-pin tqfp
copyright ? 1997 lattice semiconductor corporation. e 2 cmos, gal, ispgal, isplsi, plsi, pds, silicon forest, ultramos, lattice semiconductor, l (stylized) lattice semiconductor corp., l (stylized) and lattice (design) are registered trademarks of lattice semiconductor corporation. generic array logic, isp, ispate, ispcode, ispdownload, ispgds, ispds, ispds+, ispstarter, ispstream, isptest, ispturbo, latch-lock, pds+, rft, total isp and twin glb are trademarks of lattice semiconductor corporation. isp is a service mark of lattice semiconductor corporation. all brand names or product names mentioned are trademarks or registered trademarks of their respective holders. lattice semiconductor corporation (lsc) products are made under one or more of the following u.s. and international patents: 4,761,768 us, 4,766,569 us, 4,833,646 us, 4,852,044 us, 4,855,954 us, 4,879,688 us, 4,887,239 us, 4,896,296 us, 5,130,574 us, 5,138,198 us, 5,162,679 us, 5,191,243 us, 5,204,556 us, 5,231,315 us, 5,231,316 us, 5,237,218 us, 5,245,226 us, 5,251,169 us, 5,272,666 us, 5,281,906 us, 5,295,095 us, 5,329,179 us, 5,331,590 us, 5,336,951 us, 5,353,246 us, 5,357,156 us, 5,359,573 us, 5,394,033 us, 5,394,037 us, 5,404,055 us, 5,418,390 us, 5,493,205 us, 0194091 ep, 0196771b1 ep, 0267271 ep, 0196771 uk, 0194091 gb, 0196771 wg, p3686070.0-08 wg. lsc does not represent that products described herein are free from patent infringement or from any third-party right. the specifications and information herein are subject to change without notice. lattice semiconductor corporation (lsc) reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made. lsc recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current. lsc warrants performance of its products to current and applicable specifications in accordance with lscs standard warranty. testing and other quality control procedures are performed to the extent lsc deems necessary. specific testing of all parameters of each product is not necessarily performed, unless mandated by government requirements. lsc assumes no liability for applications assistance, customers product design, software performance, or infringements of patents or services arising from the use of the products and services described herein. lsc products are not authorized for use in life-support applications, devices or systems. inclusion of lsc products in such applications is prohibited. lattice semiconductor corporation 5555 northeast moore court hillsboro, oregon 97124 u.s.a. tel.: (503) 681-0118 fax: (503) 681-3037 http://www.latticesemi.com february 1997

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